Recently, there is a demand from the side of the market for an LSI circuit of lower power consumption. As regards an LSI circuit, such type of an LSI circuit in which the power supply for its core part is partially or wholly turned off to reduce the stand-by power is being offered to the market. There is also such a system in which, since it is not the total of the functions of the system that is to be in stand-by state, the LSI circuits other than that in a stand-by state are set into operation.
Thus, in an LSI circuit driven by a plurality of power supplies, the logic state of the LSI circuit, the power supply of which is partially turned off, needs to be in some form of a definitive state. For example, if, in an LSI circuit, the power supply of a core part of the circuit is turned off, it is necessary to maintain the power supply for an I/O part of the circuit in on-state in order to keep on supplying the power and outputting a definitive logic state of some form or other. Patent Document 1 shows such a technique in which the power supply of an I/O part is maintained in an on-state to keep on supplying the power to provide a definitive logic state of the I/O buffer with the use of a stand-by signal STBY indicating the state of the power supply voltage of the core part.
The formulation of the conventional level shifter circuit, shown in Patent Document 1, is now described with reference to FIGS. 6 and 8. A level shift circuit 30 is made up of circuit blocks 38 and 39. The circuit block 38 is run in operation as it is fed with the voltage of a power supply Va over a power supply line 35. The circuit block 39 is run in operation as it is fed with the voltage of a power supply Vb over a power supply line 36 and as it receives a signal from the circuit block 38. Meanwhile, the circuit blocks 38, 39 are connected common to a ground line 37 as a reference voltage of the power supply voltages Va and Vb. In the circuit block 39, a level converter circuit 40 is formed by N-channel MOS transistors Q7, Q8 and P-channel MOS transistors Q9, Q10. The transistors Q7, Q8 have sources connected to the ground line 37. The transistor Q9 is connected between the power supply line 36 and the transistor Q7, while the transistor Q10 is connected between the power supply line 36 and the transistor Q8. The transistor Q9 has a gate connected to the drain of the transistor Q8, while the transistor Q10 has a gate connected to the drain of the transistor Q7. The drains of the transistors Q8, Q10 serve as an output terminal of the level converter circuit 40. An output signal of the level converter circuit 40 is delivered as Dout via a NAND gate 41, operating as a level determining circuit, and via an inverter 42. A sleep signal SLP is delivered via inverters 43, 44 to the circuit block 38, while being delivered via inverter 43 to the NAND gate 41 to operate as a level determining control signal for the NAND gate 41. On the other hand, in the circuit block 38, an input signal Din and the sleep signal SLP from the inverter 44 are delivered to a NOR gate 45, while an output signal of the NOR gate 45 and the sleep signal SLP are delivered to a NOR gate 46. Output signals of the NOR gates 45, 46 are delivered to the gates of the transistors Q8, Q7, respectively. FIG. 8 shows an inner circuit of the each of the NOR gates 45, 46. These NOR gates 45, 46 are each formed by N-channel MOS transistors Q14, Q15 and P-channel MOS transistors Q16, Q17.
The operation of the level shift circuit 30 is now described. During the normal operation, the sleep signal SLP is at LOW level. Hence, the output signals of the inverters 43, 44 are respectively at HIGH level and LOW level, with the NAND gate 41 and the NOR gates 45, 46 operating as inverters. If the input data Din is at LOW level (0V), the transistors Q7, Q10 are off, while the transistors Q8, Q9 are on, with the circuit block 39 providing data Din at LOW level (0V). On the other hand, if the input data Din is at HIGH level (voltage Va), the transistors Q7, Q10 are on, while the transistors Q8, Q9 are off, with the circuit block 39 delivering the data Din at HIGH level (voltage Vb).
During the stand-by time, the sleep signal SLP is brought HIGH. A power supply circuit, not shown, ceases generation and outputting of the power supply voltage Va. At this time, the output signals of the inverters 43, 44 in the level shift circuit 30 are brought LOW and HIGH, respectively. Since the NOR gates 45, 46 of the circuit block are of the circuit configuration shown in FIG. 8, one of the transistors Q14, Q15 is turned on as long as the output signal of the inverter 44 is kept HIGH, even in case the power supply voltage Va is turned off, thus outputting a LOW level signal. This causes the transistors Q7, Q8 of the level converter circuit 40 to be turned off to inhibit the tunneling current that might otherwise flow from the power supply line 36 via transistors Q9, Q7 to the grounding line 37 as well as the tunneling current that might otherwise flow from the power supply line 36 via transistors Q10, Q8 to the grounding line 37. At this time, the output of the level converter circuit 40 sees a high impedance and is at an indefinite level. However, the NAND gate 41 delivers an output signal fixed at a HIGH level without dependency upon the output signal level of the level converter circuit 40. Hence, the circuit block 39 is able to output the data Din fixed at LOW level (0V).
[Patent Document 1] JP Patent Kokai Publication No. JP-P2006-173889A